VLSI / VHDL / VERILOG Projects – Image Processing Based VLSI Projects

  1. A Scalable Approximate DCTArchitectures For EfficientHEVC Compliant Video Coding
  2. LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
  3. Multiplier Less Unity-Gain SDF FFTS
  4. Exploiting Adder Compressors For Power-Efficient 2-D Approximate Dct Realization
  5. Recursive Integer Cosine Transform For HEVC And Future Video Coding Standards
  6. A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
  7. A New Binary-Halved Clustering Method and ERT Processor for ASSR System
  8. The VLSI Architecture of a Highly Efficient De-blocking Filter for HEVC Systems
  9. Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals
  10. Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems
  11. Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing
  1. Optimized approach of sobel edge detection technique using Xilinx system generator
  2. Reconfigurable architecture of adaptive median filter — An FPGA based approach for impulse noise suppression
  3. High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis
  1. Area Delay Power Efficient Carry Select Adder
  2. On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
  3. Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
  4. A Method to Extend Orthogonal Latin Square Codes
  5. Design and Estimation of delay power and area for Parallel prefix adders
  6. Design and FPGA implementation of compressor based Vedic multiplier
  7. A Combined SDC SDF Architecture for Normal I/O Pipelined Radix-2 FFT
  8. Area Delay Efficient Binary Adders in QCA
  9. Test Versus Security Past and Present
  10. Skewed Load Test Cubes Based on Functional Broadside Tests for a Low Power Test Set
  11. High Speed Convolution and De convolution Algorithm
  12. Fast Radix 10 Multiplication Using Redundant BCD Codes
  13. Low Complexity Low Latency Architecture for Matching of Data Encoded With Hard Systematic Error Correcting Codes
  14. Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing
  15. Design of High Performance 64 bit MAC Unit
  16. Thwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison
  17. Low Power Test Generation by Merging of Functional Broadside Test Cubes
  18. Design of Dedicated Reversible Quantum Circuitry for Square Computation
  19. A Look Ahead Clock Gating Based on Auto Gated Flip Flops
  20. A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)
  21. Aging Aware Reliable Multiplier Design With Adaptive Hold Logic
  22. An Accuracy Adjustment Fixed Width Booth Multiplier Based on Multilevel Conditional Probability
  23. Arithmetic Based Binary to RNS Converter Modulo {2n ± k} for jn-Bit Dynamic Range
  24. Critical Path Analysis and Low Complexity Implementation of the LMS Adaptive Algorithm
  25. Design Flow for Flip Flop Grouping in Data Driven Clock Gating
  26. Design of Efficient Binary Comparators in Quantum Dot Cellular Automata
  27. Efficient Hardware Implementation of Encoder and Decoder for Golay Code
  28. Efficient Integer DCT Architectures for HEVC
  29. Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}
  30. Fault Tolerant Parallel Filters Based on Error Correction Codes
  31. Low Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure
  32. On the Design of Efficient Modulo 2n+1 Multiply Add Add Units
  33. Reverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations
  34. FPGA based partial reconfigurable fir filter design
  35. An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC
  36. An Efficient Field Programmable Gate ArrayImplementation of Double Precision Floating Point Multiplier using VHDL
  37. An Overview of Advance Microcontroller Bus Architecture Relate on AHB Bridge
  38. FPGA-Based Bit Error Rate PerformanceMeasurement of Wireless Systems
  1. Thwarting Scan Based Attacks on Secure ICs With On Chip Comparison
  2. Design for testablity support for launch and capture power reduction in launch of shift and launch of capture testing
  3. Area Delay Efficient Binary Adders in QCA
  4. CMOS Charge Pump With No Reversion Loss and Enhanced Drivability
  5. Efficent Register renaming and recovery for high performance Processors
  6. Low Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple
  7. Enhanced memory reliabilty against multiple cells upsets using decimal
  8. Average 8T Differential Sensing Subthreshold SRAM With Bit Interleaving
  9. Reliable Concurrent Error Detection Architectures for Extended Euclidean
  10. CORDIC Designs for Fixed Angle of Rotation
  11. A Built In Repair Analyzer With Optimal Repair Rate for Word Oriented
  1. Low Power 10 Transistor Full Adder Design Based on Degenerate Pass Transistor
  2. Design of 64 Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic
  3. Design of low power high speed vlsi adder Subsystem
  4. Synthesis and Implementation of UART using verilog Codes
  5. HICPA A Hybrid Low Power Adder for High Performance Processors
  6. Low Power and Area Efficient Carry Select Adder
  7. Design and Implementation of Two Variable Multiplier Using KCM and Vedic
  8. Design and Implementation of a High Performance Multiplier using HDL
  9. Design of low power and high performance radix 4 multiplier
  10. High Speed and Area Efficient Vedic Multiplier
  11. Built In Generation of Functional Broadside Tests Using a Fixed Hardware
  12. Low power variation aware flipflop
  13. High speed Modified Booth Encoder multiplier for signed and unsigned
  14. An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
  15. High Speed Signed Multiplier for Digital SignalProcessing Applications
  16. Accumulator Based 3 Weight Pattern Generation
  17. Design of Low Power TPG Using LP LFSR
  18. A Real time Face Detection And Recognition System
  19. Verilog Implementation of UART with Status Register
  20. FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
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