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VLSI / VHDL / Verilog (267)

MTech Projects offering final year VLSI VHDL Verilog MTech Projects, VLSI VHDL Verilog IEEE Projects, IEEE VLSI VHDL Verilog Projects, VLSI VHDL Verilog MS Projects, VLSI VHDL Verilog BTech Projects, VLSI VHDL Verilog BE Projects, VLSI VHDL Verilog ME Projects, VLSI VHDL Verilog IEEE Projects, VLSI VHDL Verilog IEEE Basepapers, VLSI VHDL Verilog Final Year Projects, VLSI VHDL Verilog Academic Projects, VLSI VHDL Verilog Projects, VLSI VHDL Verilog Seminar Topics, VLSI VHDL Verilog Free Download Projects, VLSI VHDL Verilog Free Projects in Hyderabad, Bangalore, Chennai and Delhi, India.

A Cellular Network Architecture WithPolynomial Weight Functions – 2016

Emulations of cellular nonlinear networks on digital reconfigurable hardware are renowned for an economical computation of huge knowledge, exceeding the accuracy and adaptability of full-custom

A Novel Coding Scheme for Secure Communications in Distributed RFID Systems – 2016

Privacy protection is the primary concern when RFID applications are deployed in our daily lives. Due to the computational power constraints of passive tags, non-encryption-based

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits – 2016

Single error correction (SEC) codes are widely used to protect information stored in recollections and registers. In some applications, such as networking, some management bits

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers – 2016

During this paper, we style a hardware and energy-economical stochastic lower-higher decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the advanced arithmetic

Memory-Reduced Turbo Decoding ArchitectureUsing NII Metric Compression – 2016

This brief proposes a replacement compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed theme stores only the

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers – 2016

This transient proposes an on-line clear take a look at technique for detection of latent onerous faults which develop in 1st-input first-output buffers of routers

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks – 2016

Soft errors pose a reliability threat to fashionable electronic circuits. This makes protection against soft errors a demand for many applications. Communications and signal processing

A New XOR-Free Approach for Implementation of Convolutional Encoder – 2016

This letter presents a new algorithm to construct an XOR-Free architecture of an influence efficient Convolutional Encoder. Optimization of XOR operators is the most concern

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code – 2016

Memories that operate in harsh environments, like for instance space, suffer a important variety of errors. The error correction codes (ECCs) are routinely used to

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic – 2016

This paper proposes a high-throughput energy-economical Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at comparatively

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