VLSI / VHDL / Verilog (267)

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A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits – 2016

Single error correction (SEC) codes are widely used to protect information stored in recollections and registers. In some applications, such as networking, some management bits

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers – 2016

During this paper, we style a hardware and energy-economical stochastic lower-higher decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the advanced arithmetic

Memory-Reduced Turbo Decoding ArchitectureUsing NII Metric Compression – 2016

This brief proposes a replacement compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed theme stores only the

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers – 2016

This transient proposes an on-line clear take a look at technique for detection of latent onerous faults which develop in 1st-input first-output buffers of routers

A Cellular Network Architecture WithPolynomial Weight Functions – 2016

Emulations of cellular nonlinear networks on digital reconfigurable hardware are renowned for an economical computation of huge knowledge, exceeding the accuracy and adaptability of full-custom

A Novel Coding Scheme for Secure Communications in Distributed RFID Systems – 2016

Privacy protection is the primary concern when RFID applications are deployed in our daily lives. Due to the computational power constraints of passive tags, non-encryption-based

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code – 2016

Memories that operate in harsh environments, like for instance space, suffer a important variety of errors. The error correction codes (ECCs) are routinely used to

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic – 2016

This paper proposes a high-throughput energy-economical Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at comparatively

A New CDMA Encoding/Decoding Method for on-Chip Communication Network – 2016

As a high performance on-chip communication methodology, the code division multiple access (CDMA) technique has recently been applied to networks on chip (NoCs). We have

An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding – 2016

In numerous memory and communication systems, Bose-Chaudhuri-Hocquenghem (BCH) codes are widely used to reinforce reliability. One-pass Chase soft-call decoding algorithm for BCH code was previously

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