MTech Projects offering final year Electronics MTech Projects, Electronics IEEE Projects, IEEE Electronics Projects, Electronics MS Projects, Electronics BTech Projects, Electronics BE Projects, Electronics ME Projects, Electronics IEEE Projects, Electronics IEEE Base Papers, Electronics Final Year Projects, Electronics Academic Projects, Electronics Projects, Electronics Seminar Topics, Electronics Free Download Projects, Electronics Free Projects in Hyderabad, Bangalore, Chennai and Delhi, India.

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits – 2016

Single error correction (SEC) codes are widely used to protect information stored in recollections and registers. In some applications, such as networking, some management bits

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers – 2016

During this paper, we style a hardware and energy-economical stochastic lower-higher decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the advanced arithmetic

Memory-Reduced Turbo Decoding ArchitectureUsing NII Metric Compression – 2016

This brief proposes a replacement compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed theme stores only the

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers – 2016

This transient proposes an on-line clear take a look at technique for detection of latent onerous faults which develop in 1st-input first-output buffers of routers

A Cellular Network Architecture WithPolynomial Weight Functions – 2016

Emulations of cellular nonlinear networks on digital reconfigurable hardware are renowned for an economical computation of huge knowledge, exceeding the accuracy and adaptability of full-custom

A Novel Coding Scheme for Secure Communications in Distributed RFID Systems – 2016

Privacy protection is the primary concern when RFID applications are deployed in our daily lives. Due to the computational power constraints of passive tags, non-encryption-based

An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding – 2016

In numerous memory and communication systems, Bose-Chaudhuri-Hocquenghem (BCH) codes are widely used to reinforce reliability. One-pass Chase soft-call decoding algorithm for BCH code was previously

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols – 2016

In a fashionable system-on-chip design, tons of cores and intellectual properties can be integrated into a single chip. To be appropriate for top-performance interconnects, designers

An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA – 2016

A high performance substitution box (S-Box) FPGA implementation using Galois Field GF (28) is presented in this paper. An optimum variety of pipeline registers based

Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames – 2016

Radiation-induced multiple bit upsets (MBUs) are a serious reliability concern in nanoscale technology nodes. Occurrence of such errors within the configuration frames of a field-programmable

Page 1 of 361 2 3 36

Facebook Friends