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VLSI Testing Projects

V17TEST01COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits2017
V17TEST02Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding2017
V17TEST03Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST2017
V17TEST04Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares2017
V17TEST05High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations2017
V17TEST06An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA2017
V17TEST07LFSR-Based Generation of Multi cycle Tests2017
V16TEST01Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories2016
V16TEST02A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis2016
V16TEST03Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST2016
V16TEST04Design for Testability of Sleep Convention Logic2016
V16TEST05Computing Seeds for LFSR-Based Test Generation From Non test Cubes2016
V15TEST01A novel realization of reversible LFSR for its application in cryptography2015
V15TEST02Preemptive Built-In Self-Test for In-Field Structural Testing2015
V15TEST03Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment2015
V15TEST04Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures2015
V15TEST05Multiplexer based High Throughput S-box for AES Application2015
V15TEST06Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set2015
V15TEST07A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults2015
V15TEST08Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL2015