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VLSI IEEE PROJECTS 2018 – 19 for MTech Students

VLSI IEEE Projects for Masters degree, BE, BTech, ME, MTech final Year Academic Submission. VLSI Thesis for PhD and Research Students. Download complete VLSI Project Code with Full Report, PDF, PPT, Tutorial, Documentation, VLSI Research paper and Thesis Work.

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Latest 2018-2019 VLSI Project topics for M.Tech Students:

S.NOPROJECT TITLEYEAR   
VLSI18G01Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique2018
VLSI18G02Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications2018
VLSI18G03Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic2018
VLSI18G04Effect of Switched-Capacitor CMFB on the Gain of Fully Differential OpAmp for Design of Integrators2018
VLSI18G05Passive Noise Shaping in SAR ADC With Improved Efficiency2018
VLSI18G06A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm2018
VLSI18G07Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique2018
VLSI18G08Low Power 4_4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder2018
VLSI18G09Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates2018
VLSI18G10Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation2018
VLSI18G11A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS2018
VLSI18G12A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators2018
VLSI18G13A Highly Efficient Composite Class-ABÐAB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads2018
VLSI18G14Approximate Quaternary Addition with the Fast Carry Chains of FPGAs2018
VLSI18G15A Low-Power Configurable Adder for Approximate Applications2018
VLSI18G16A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design2018
VLSI18G17A Low-Power Yet High-Speed Configurable Adder for Approximate Computing2018
VLSI18G18A Simple Yet Efficient Accuracy- Configurable Adder Design2018
VLSI18G19Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design2018
VLSI18G20Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers2018
VLSI18G21A Cost-Effective Self-Healing Approach for Reliable Hardware Systems2018
VLSI18G22Approximate Sum-of-Products Designs Based on Distributed Arithmetic2018
VLSI18G23Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications2018
VLSI18G24Design, Evaluation and Application of Approximate High-Radix Dividers2018
VLSI18G25Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors2018
VLSI18G26Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits2018
VLSI18G27Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors2018
VLSI18G28Inexact Arithmetic Circuits for Energy Efficient loT Sensors Data Processing2018
VLSI18G29Low-Power Addition with Borrow-Save Adders under Threshold Voltage Variability2018
VLSI18G30Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system2018
VLSI18G31On the Difficulty of Inserting Trojans in Reversible Computing Architectures2018
VLSI18G32Optimizing Power-Accuracy trade-off in Approximate Adders2018
VLSI18G33Power Efficient Approximate Booth Multiplier2018
VLSI18G34Reducing the Hardware Complexity of a Parallel Prefix Adder2018
VLSI18G35Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder2018
VLSI18G36Towards Efficient Modular Adders based on Reversible Circuits2018
VLSI18G37A 32-bit 4_4 Bit-Slice RSFQ Matrix Multiplier2018
VLSI18G38Research and implementation of hardware algorithms for multiplying binary numbers2018
VLSI18G39Efficient Design for Fixed-Width Adder-Tree2018
VLSI18G40Architecture Generator for Type-3 Unum Posit Adder/Subtractor2018
VLSI18G41An Efficient FPGA Implementation of HEVC Intra Prediction2018
VLSI18G42An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators2018
VLSI18G43Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic2018
VLSI18G44VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors2018
VLSI18G45A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test2018
VLSI18G46Automotive Functional Safety Assurance by POST with Sequential Observation2018
VLSI18G47Flexible Architecture of Memory BISTs2018
VLSI18G48Logic BIST with Capture-per-Clock Hybrid Test Points2018
VLSI18G49Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation2018
VLSI18G50Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications2018
VLSI18G51A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits2018
VLSI18G52Efficient Implementations of 4-Bit Burst Error Correction for Memories2018
VLSI18G53Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction2018
VLSI18G54Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design2018
VLSI18G55Basic-Set Trellis MinÐMax Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields2018
VLSI18G56An Efficient VLSI Architecture for Convolution Based DWT Using MAC2018
VLSI18G57Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method2018
VLSI18G58Reconfigurable Decoder for LDPC and Polar Codes2018
VLSI18G59Design and simulation of CRC encoder and decoder using VHDL2018
VLSI18G60Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add2018
VLSI18G61Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors2018
VLSI18G62Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences2018
VLSI18G63Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter2018
VLSI18G64FIR Filter Design Based On FPGA2018
VLSI18G65Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters2018
VLSI18G66A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation2018
VLSI18G67An Approach to LUT Based Multiplier for Short Word Length DSP Systems2018
VLSI18G68EEG Signal Denoising based on Wavelet Transform using Xilinx System Generator2018
VLSI18G69FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications2018
VLSI18G70Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption2018
VLSI18G71Unbiased Rounding for HUB Floating-point Addition2018
VLSI18G72The Design and Implementation of Multi Ð Precision Floating Point Arithmetic Unit Based on FPGA2018
VLSI18G73Chip Design for Turbo Encoder Module for In-Vehicle System2018
VLSI18G74Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks2018
VLSI18G75MAES: Modified Advanced Encryption Standard for Resource Constraint Environments2018
VLSI18G76Binary To Gray Code Converter Implementation Using QCA2018
VLSI18G77A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)2018
VLSI18G78A Novel Five-input Multiple-function QCA Threshold Gate2018
VLSI18G79A Low-Power High-Speed Comparator for Precise Applications2018
VLSI18G80A High Performance Gated Voltage Level Translator with Integrated Multiplexer2018
VLSI18G81High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop2018
VLSI18G82Fractional- Order Differentiators and Integrators with Reduced Circuit Complexity2018
VLSI18G83Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis2018
S.NOPROJECT TITLEYEAR   
VLSI17G01High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes2017
VLSI17G02A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation2017
VLSI17G03A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers2017
VLSI17G04Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers2017
VLSI17G05Design of Power and Area Efficient Approximate Multipliersc2017
VLSI17G06Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing2017
VLSI17G07Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx2017
VLSI17G08Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity2017
VLSI17G09A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n_ 1, 2n+ 1, 22n+ 1, 22n+p}2017
VLSI17G10Fast Energy Efficient Radix-16 Sequential Multiplier2017
VLSI17G11DSP48E Efficient Floating Point Multiplier Architectures on FPGA2017
VLSI17G12Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems2017
VLSI17G13Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic2017
VLSI17G14Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication2017
VLSI17G15Design and Analysis of Multiplier Using Approximate 15-4 Compressor2017
VLSI17G16Energy-Efficient Approximate Multiplier Design usingBit Significance-Driven Logic Compression2017
VLSI17G17High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder2017
VLSI17G18Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction2017
VLSI17G19Multi-operand logarithmic addition/subtraction based on Fractional Normalization2017
VLSI17G20On the Implementation of Computation-in-Memory Parallel Adder2017
VLSI17G21Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor2017
VLSI17G22Probabilistic Error Analysis of Approximate Recursive Multipliers2017
VLSI17G23RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder2017
VLSI17G24RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing2017
VLSI17G25Comparative study of 16-order FIR filter design using different multiplication techniques2017
VLSI17G26An Optimised 3x3 Shift and Add Multiplier on FPGA2017
VLSI17G27Optimization of Constant Matrix Multiplication with Low Power and High Throughput2017
VLSI17G28Realization of a hardware generator for the Sum of Absolute Difference component2017
VLSI17G29A Structured Visual approach to GALS Modellingand Verification of Communication Circuits2017
VLSI17G30A Novel Data Format for Approximate Arithmetic Computing2017
VLSI17G31Area-Efficient Architecture for Dual-Mode DoublePrecision Floating Point Division2017
VLSI17G32DLAU: A Scalable Deep Learning Accelerator Uniton FPGA2017
VLSI17G33Reconfigurable Constant Multiplication for FPGAs2017
VLSI17G34Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs2017
VLSI17G35Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields2017
VLSI17G36Efficient Designs of Multi ported Memory on FPGA2017
VLSI17G37On the VLSI Energy Complexityof LDPC Decoder Circuits2017
VLSI17G38A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes2017
VLSI17G39A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices2017
VLSI17G40Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding2017
VLSI17G41Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST2017
VLSI17G4228-nm Latch-Type Sense Amplifier Modification for Coupling Suppression2017
VLSI17G43A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA2017
VLSI17G44CMCS: Current-Mode Clock Synthesis2017
VLSI17G45Binary Adder Circuit Design Using Emerging MIGFET Devices2017
VLSI17G46A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier2017
VLSI17G47A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications2017
VLSI17G48Delay Analysis for Current Mode Threshold Logic Gate Designs2017
VLSI17G49A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar2017
VLSI17G50A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies2017
VLSI17G51A Memristor Based Binary Multiplier2017
VLSI17G52Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications2017
VLSI17G53Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays2017
VLSI17G54Design and Low Power Magnitude Comparator2017
VLSI17G55Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders2017
VLSI17G56Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology2017
VLSI17G57High Performance Ternary Adder using CNTFET2017
VLSI17G58High-performance engineered gate transistor-based compact digital circuits2017
VLSI17G59Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops2017
VLSI17G60Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits2017
VLSI17G61Optimized Memristor-Based Multipliers2017
VLSI17G62Probability-Driven Multibit Flip-Flop Integration With Clock Gating2017
VLSI17G63Register Ð Less NULL Conventional Logic2017
VLSI17G64Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template2017
VLSI17G65Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design2017
VLSI17G6610T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage2017
VLSI17G67Fault Tolerant Logic Cell FPGA2017
VLSI17G68A band-selective low-noise amplifier using an improved tunable active inductor for 3Ð5 GHz UWB receivers2017
VLSI17G69A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply2017
VLSI17G70A Low Power, Low Noise Amplifier For Recording Neural Signals amplification in SCL 180nm2017
VLSI17G71A Single-ended with Dynamic Feedback Control 8T Sub threshold SRAM Cell2017
VLSI17G72Analysis and Design of the Classical CMOS Schmitt Trigger in Sub threshold Operation2017
VLSI17G73Design And Analysis Of Combinational Coding Circuits Using Adiabatic Logic2017
VLSI17G74Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology2017
VLSI17G75Evolutionary Approach to Approximate Digital Circuits Design2017
VLSI17G76Low Power 8-bit ALU Design Using Full Adder and Multiplexer2017
VLSI17G77Powering Wearable Sensors with a Low-Power CMOS Piezoelectric Energy Harvesting Circuit2017
VLSI17G78Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression2017
VLSI17G79Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm2017
VLSI17G80A Structured Visual approach to GALS Modelling and Verification of Communication Circuits2017
VLSI17G81Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials2017
VLSI17G82Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division2017
VLSI17G83High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA2017
VLSI17G84DLAU: A Scalable Deep Learning Accelerator Unit on FPGA2017
VLSI17G85Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz MatrixÐVector Product Decomposition2017
VLSI17G86Area-time Efficient Architecture of FFT-based Montgomery Multiplication2017
VLSI17G87Efficient RNS Scalers for the Extended Three-Moduli Set(2n -1; 2n+p; 2n + 1)2017
VLSI17G88Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities2017
VLSI17G89Design and Applications of Approximate Circuits by Gate-Level Pruning2017
VLSI17G90Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM2017
VLSI17G91Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic2017
VLSI17G92Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters2017
VLSI17G93A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC2017
VLSI17G94Design of Efficient Multiplier less Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation2017
VLSI17G95Software Implementation of the Recursive Discrete Fourier Transform2017
VLSI17G96COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits2017
VLSI17G97Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares2017
VLSI17G98High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations2017
VLSI17G99An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA2017
VLSI17G100LFSR-Based Generation of Multi cycle Tests2017
VLSI17G101Overloaded CDMA Crossbar for Network-On-Chip2017
VLSI17G102A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator2017
VLSI17G103A Custom Accelerator for Homomorphic Encryption Applications2017
VLSI17G104A novel method of decoding the BCH code based on norm syndrome to improve the error correction efficiency2017
VLSI17G105An Efficient O(N) Comparison-Free Sorting Algorithm2017
VLSI17G106Efficient Soft Cancelation Decoder Architectures for Polar Codes2017
VLSI17G107Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-like Block Ciphers2017
VLSI17G108Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications2017
VLSI17G109Low Redundancy Matrix-Based codes for Adjacent Error Correction with Parity Sharing2017
VLSI17G110Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices2017
VLSI17G111Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping2017
VLSI17G112Probabilistic Error Modeling for Approximate Adders2017
VLSI17G113Novel Solutions of Delta-Sigma Based Rectifying Encoder2017
VLSI17G114SPARX - A Side-Channel Protected Processor for ARX-based Cryptography2017
VLSI17G115LLR-based Successive-Cancellation List Decoder for Polar Codes with Multi-bit Decision2017
VLSI17G116Towards Low Power Approximate DCT Architecture for HEVC Standard2017
VLSI17G117High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder2017
VLSI17G118Two Approximate Voting Schemes for Reliable Computing2017
VLSI17G119Two-Extra-Column Trellis MinÐMax Decoder Architecture for Nonbinary LDPC Codes2017
VLSI17G120Key Reconciliation Protocols for Error Correction of Silicon PUF Responses2017
VLSI17G121Code Compression for Embedded Systems Using Separated Dictionaries2017
VLSI17G122A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding2017
VLSI17G123High Performance Integer DCT Architectures For HEVC2017
VLSI17G124Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities2017
VLSI17G125A Scalable Approximate DCT Architectures For Efficient HEVC Compliant Video Coding2017
VLSI17G126Multiplier less Unity-Gain SDF-FFTS2017
VLSI17G127Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique2017
VLSI17G128Scenario-Aware Dynamic Power Reduction Using Bias Addition2017
VLSI17G129Clock-gating of streaming applications for energy efficient implementations on FPGAs2017
VLSI17G130Operating Frequency Improvement On FPGA Implementation Of A Pipeline Large-FFT Processor2017
VLSI17G131Design of Efficient Programmable Test-per-Scan Logic BIST Modules2017
VLSI17G132Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA2017
VLSI17G133Design of Efficient BCD Adders in Quantum-Dot Cellular Automata2017
VLSI17G134Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit2017
VLSI17G13512T Memory Cell for Aerospace Applications in Nano scale CMOS Technology2017