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VLSI FPGA IEEE Projects 2018 – 19 for MTech Students

VLSI FPGA IEEE Projects for Masters degree, BE, BTech, ME, MTech final Year Academic Submission. VLSI FPGA Thesis for PhD and Research Students. Download complete VLSI FPGA Project Code with Full Report, PDF, PPT, Tutorial, Documentation, VLSI FPGA Research paper and Thesis Work.

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Latest 2018-2019 VLSI FPGA Project topics for M.Tech Students:

S.NOPROJECT TITLEYEAR   
V17FPG01High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes2017
V17FPG02A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation2017
V17FPG03A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers2017
V17FPG04Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers2017
V17FPG05Design of Power and Area Efficient Approximate Multipliersc2017
V17FPG06Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing2017
V17FPG07Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx2017
V17FPG08Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity2017
V17FPG09A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n_ 1, 2n+ 1, 22n+ 1, 22n+p}2017
V17FPG10Fast Energy Efficient Radix-16 Sequential Multiplier2017
V17FPG11DSP48E Efficient Floating Point Multiplier Architectures on FPGA2017
V17FPG12Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems2017
V17FPG13Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic2017
V17FPG14Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication2017
V17FPG15Design and Analysis of Multiplier Using Approximate 15-4 Compressor2017
V17FPG16Energy-Efficient Approximate Multiplier Design usingBit Significance-Driven Logic Compression2017
V17FPG17High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder2017
V17FPG18Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction2017
V17FPG19Multi-operand logarithmic addition/subtraction based on Fractional Normalization2017
V17FPG20On the Implementation of Computation-in-Memory Parallel Adder2017
V17FPG21Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor2017
V17FPG22Probabilistic Error Analysis of Approximate Recursive Multipliers2017
V17FPG23RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder2017
V17FPG24RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing2017
V17FPG25Comparative study of 16-order FIR filter design using different multiplication techniques2017
V17FPG26An Optimised 3x3 Shift and Add Multiplier on FPGA2017
V17FPG27Optimization of Constant Matrix Multiplication with Low Power and High Throughput2017
V17FPG28Realization of a hardware generator for the Sum of Absolute Difference component2017
V17FPG29A Structured Visual approach to GALS Modellingand Verification of Communication Circuits2017
V17FPG30A Novel Data Format for Approximate Arithmetic Computing2017
V17FPG31Automatic Generation of Farmally Prover temper resistant Galioes field multiplier based on generalized masking scheme2017
V17FPG32Area-Efficient Architecture for Dual-Mode DoublePrecision Floating Point Division2017
V17FPG33DLAU: A Scalable Deep Learning Accelerator Uniton FPGA2017
V17FPG34Reconfigurable Constant Multiplication for FPGAs2017
V17FPG35Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs2017
V17FPG36Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields2017
V17FPG37Efficient Designs of Multi ported Memory on FPGA2017
V17FPG38Two Approximate Voting Schemes for Reliable Computing2017
V17FPG39On the VLSI Energy Complexityof LDPC Decoder Circuits2017
V17FPG40Two-Extra-Column Trellis MinÐMax Decoder Architecture for Nonbinary LDPC Codes2017
V17FPG41A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes2017
V17FPG42A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices2017
V17FPG43Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding2017
V17FPG44Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST2017