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VLSI DSP Applications Projects

S.NOPROJECT TITLEYEAR   
V17DSP01A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes2017
V17DSP02Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities2017
V17DSP03Design and Applications of Approximate Circuits by Gate-Level Pruning2017
V17DSP04A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices2017
V17DSP05Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM2017
V17DSP06High Performance Integer DCT Architectures for HEVC2017
V17DSP07Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic2017
V17DSP08Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters2017
V17DSP09A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC2017
V17DSP10Design of Efficient Multiplier less Modified Cosine-Based Comb Decimation Filters: Analysis and Implementation2017
V17DSP11Software Implementation of the Recursive Discrete Fourier Transform2017
S.NOPROJECT TITLEYEAR   
V16DSP01A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO2016
V16DSP02Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units2016
V16DSP03A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications2016
V16DSP04Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing2016
V16DSP05Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems2016
V16DSP06A Mixed-Decimation MDF Architecturefor Radix-2k Parallel FFT2016
V16DSP07A High-Speed FPGA Implementation of an RSD-Based ECC Processor2016
V16DSP08A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling2016
V16DSP09Code Compression for Embedded Systems Using Separated Dictionaries2016
V16DSP10A Dynamically Reconfigurable Multi-ASIP Architecture for Multi-standard and Multimode Turbo Decoding2016
V16DSP11Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order2016
V16DSP12Statistical Framework and Built-In Self Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators2016
V16DSP13A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones2016
V16DSP14Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication2016
V16DSP15A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register2016
V16DSP16GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis2016
V16DSP17An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop2016
V16DSP18Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics2016
S.NOPROJECT TITLEYEAR   
V15DSP01A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT2015
V15DSP02A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications2015
V15DSP03An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC2015
V15DSP04Obfuscating DSP Circuits via High-Level Transformations2015
V15DSP05Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing2015
V15DSP06Data Encoding Techniques for Reducing EnergyConsumption in Network-on-Chip2015
V15DSP07New Lightweight AES S-box Using LFSR2015
V15DSP08A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply2015
V15DSP09A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications2015
V15DSP10A Low-Complexity Multiple Error CorrectingArchitecture Using Novel Cross ParityCodes Over GF(2m).2015
V15DSP11Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic2015
V15DSP12Algorithm and Architecture for a Low-PowerContent-Addressable Memory Basedon Sparse Clustered Networks2015
V15DSP13An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary CommonSub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis.2015
V15DSP14Byte-Reconfigurable LDPC Codec DesignWith Application to High-Performance ECC ofNAND Flash Memory Systems2015
V15DSP15Implementation of Sub-threshold AdiabaticLogic for Ultralow-Power Application2015