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VLSI Core Projects

S.NOPROJECT TITLEYEAR   
V17CORE01A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation2017
V17CORE02A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers2017
V17CORE03Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers2017
V17CORE04Design of Power and Area Efficient Approximate Multipliers2017
V17CORE05Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing2017
V17CORE06Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx2017
V17CORE07Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity2017
V17CORE08A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n _ 1, 2n + 1, 22n + 1, 22n+p}2017
V17CORE09Fast Energy Efficient Radix-16 Sequential Multiplier2017
V17CORE10DSP48E Efficient Floating Point Multiplier Architectures on FPGA2017
V17CORE11Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems2017
V17CORE12Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic2017
V17CORE13Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication2017
V17CORE14Design and Analysis of Multiplier Using Approximate 15-4 Compressor2017
V17CORE15Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression2017
V17CORE16High Performance Parallel Decimal Multipliers using Hybrid BCD Codes2017
V17CORE17High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder2017
V17CORE18Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction2017
V17CORE19Multi-operand logarithmic addition/subtraction based on Fractional Normalization2017
V17CORE20On the Implementation of Computation-in-Memory Parallel Adder2017
V17CORE21Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor2017
V17CORE22Probabilistic Error Analysis of Approximate Recursive Multipliers2017
V17CORE23RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder2017
V17CORE24RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing2017
V17CORE25Comparative study of 16-order FIR filter design using different multiplication techniques2017
V17CORE26Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm2017
V17CORE27An Optimised 3x3 Shift and Add Multiplier on FPGA2017
V17CORE28Optimization of Constant Matrix Multiplication with Low Power and High Throughput2017
V17CORE29Realization of a hardware generator for the Sum of Absolute Difference component2017
V17CORE30A Structured Visual approach to GALS Modelling and Verification of Communication Circuits2017
V17CORE31Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials2017
V17CORE32A Novel Data Format for Approximate Arithmetic Computing2017
V17CORE33Automatic Generation of Farmally Prover temper resistant Galioes field multiplier based on generalized masking scheme2017
V17CORE34Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division2017
V17CORE35High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA2017
V17CORE36DLAU: A Scalable Deep Learning Accelerator Unit on FPGA2017
V17CORE37Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz MatrixÐVector Product Decomposition2017
V17CORE38Reconfigurable Constant Multiplication for FPGAs2017
V17CORE39Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs2017
V17CORE40Area-time Efficient Architecture of FFT-based Montgomery Multiplication2017
V17CORE41Efficient RNS Scalers for the Extended Three-Moduli Set(2n -1; 2n+p; 2n + 1)2017
S.NOPROJECT TITLEYEAR   
V16CORE01A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System2016
V16CORE02An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA2016
V16CORE03An Improved Signed Digit Representation Approach for Constant Vector Multiplication2016
V16CORE04Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach2016
V16CORE05Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design2016
V16CORE06Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs2016
V16CORE07Logic Synthesis in Reversible PLA2016
V16CORE08MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding2016
V16CORE09Multi Precision Arithmetic Adders2016
V16CORE10Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit2016
V16CORE11High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels2016
V16CORE12Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios2016
V16CORE13Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m)2016
V16CORE14Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest2016
V16CORE15Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic2016
V16CORE16A Modified Partial Product Generator for Redundant Binary Multipliers2016
V16CORE17Arithmetic algorithms for extended precisionusing floating-point expansions2016
V16CORE18Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding2016
V16CORE19Performance/Power Space Exploration for Binary64 Division Units2016
V16CORE20On Efficient Retiming of Fixed-Point Circuits2016
V16CORE21Hybrid LUT/Multiplexer FPGA Logic Architectures2016
V16CORE22VLSI Design for Convolutive BlindSource Separation2016
V16CORE23Concept, Design, and Implementation of Reconfigurable CORDIC2016
V16CORE24Ultralow-Energy Variation-Aware Design: Adder Architecture Study2016
V16CORE25Floating-Point Butterfly Architecture Based on Binary SignedDigit Representation2016
V16CORE26Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier2016
V16CORE27Design and Analysis of Inexact Floating-Point Adders2016
V16CORE28Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication2016
V16CORE29High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier2016
V16CORE30Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding2016
V16CORE31Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes2016
V16CORE32A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory2016
V16CORE33Implementing Minimum-Energy-Point Systems With Adaptive Logic2016
V16CORE34High-Performance NB-LDPC Decoder With Reduction of Message Exchange2016
V16CORE35Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device2016
V16CORE36Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors2016
V16CORE37Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application2016
V16CORE38Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range2016
V16CORE39Understanding the Relation Between the Performance and Reliability of NAND Flash/SCM Hybrid Solid-State Drive2016
V16CORE40Optimized Built-In Self-Repair for Multiple Memories2016
V16CORE41A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm2016
V16CORE42Network-on-Chip for Turbo Decoders2016
V16CORE43Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation2016
V16CORE44Speculative Look ahead for Energy-Efficient Microprocessors2016
V16CORE45Efficient Synchronization for Distributed Embedded Multiprocessors2016
V16CORE46NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices2016
V16CORE47A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies2016
V16CORE48Knowledge-Based Neural Network Model for FPGA Logical Architecture Development2016
V16CORE49A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes2016
V16CORE50A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing2016
V16CORE51Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems2016
V16CORE52Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division2016
V16CORE53Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching2016
V16CORE54Trigger-Centric Loop Mapping on CGRAs2016
V16CORE55Area-Aware Cache Update Trackers for Post silicon Validation2016
V16CORE56PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash2016
V16CORE57Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures2016
S.NOPROJECT TITLEYEAR   
V15CORE01Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic2015
V15CORE02A Modified Partial Product Generator for Redundant Binary Multipliers2015
V15CORE03Design & Analysis of 16 bit RISC Processor Using low Power Pipelining2015
V15CORE04Design and Analysis of Approximate Compressors for Multiplication2015
V15CORE05Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics2015
V15CORE06Design and implementation of fast floating point multiplier unit2015
V15CORE07Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA2015
V15CORE08Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata2015
V15CORE09Design of area and power aware reduced Complexity Wallace Tree multiplier2015
V15CORE10Design of area and power efficient digital FIR filter using modified MAC unit2015
V15CORE11Design of low power and high speed Carry Select Adder using Brent Kung adder2015
V15CORE12Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications2015
V15CORE13FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers2015
V15CORE14FPGA implementation of vedic floating point multiplier2015
V15CORE15FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier2015
V15CORE16High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels2015
V15CORE17FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration2015
V15CORE18Intelligent and Adaptive Traffic Light Controller using FPGA2015
V15CORE19Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication2015
V15CORE20Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications2015
V15CORE21A High-Speed FPGA Implementation of an RSD-Based ECC Processor2015
V15CORE22Analysis of ternary multiplier using booth encoding technique2015
V15CORE23A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM2015
V15CORE24HMFPCC - Hybrid-mode floating point conversion co-processor2015
V15CORE25On the Analysis of Reversible Booth's Multiplier2015
V15CORE26Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding2015
V15CORE27Reverse Converter Design via Parallel-Prefix Adders Novel Components, Methodology, and Implementations2015
V15CORE28Coming SoonRevisiting Central Limit Theorem Accurate Gaussian Random Number Generation in VLSI2015
V15CORE29Advanced low power RISC processor design using MIPS instruction set2015
V15CORE30RTL implementation for AMBA ASB APB protocol at system on chip level2015
V15CORE31Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications2015
V15CORE32Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs2015
V15CORE33Truncated ternary multipliers2015
V15CORE34An_efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm2015