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VLSI Backend Projects

S.NOPROJECT TITLEYEAR   
V17BEND0128-nm Latch-Type Sense Amplifier Modification for Coupling Suppression2017
V17BEND02A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA2017
V17BEND03CMCS: Current-Mode Clock Synthesis2017
V17BEND04Binary Adder Circuit Design Using Emerging MIGFET Devices2017
V17BEND05A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier2017
V17BEND06A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications2017
V17BEND07Delay Analysis for Current Mode Threshold Logic Gate Designs2017
V17BEND08A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar 2017
V17BEND09A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies 2017
V17BEND10A Memristor Based Binary Multiplier2017
V17BEND11Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications 2017
V17BEND12Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays 2017
V17BEND13Design and Low Power Magnitude Comparator 2017
V17BEND14Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders 2017
V17BEND15Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology 2017
V17BEND16High Performance Ternary Adder using CNTFET 2017
V17BEND17High-performance engineered gate transistor-based compact digital circuits 2017
V17BEND18Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops 2017
V17BEND19Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits 2017
V17BEND20Optimized Memristor-Based Multipliers 2017
V17BEND21Probability-Driven Multibit Flip-Flop Integration With Clock Gating 2017
V17BEND22Register – Less NULL Conventional Logic 2017
V17BEND23Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template 2017
V17BEND24Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design 2017
V17BEND2510T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage 2017
V17BEND26Fault Tolerant Logic Cell FPGA2017