| V17BEND01 | 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression | 2017 | | | |
| V17BEND02 | A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA | 2017 | | | |
| V17BEND03 | CMCS: Current-Mode Clock Synthesis | 2017 | | | |
| V17BEND04 | Binary Adder Circuit Design Using Emerging MIGFET Devices | 2017 | | | |
| V17BEND05 | A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier | 2017 | | | |
| V17BEND06 | A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications | 2017 | | | |
| V17BEND07 | Delay Analysis for Current Mode Threshold Logic Gate Designs | 2017 | | | |
| V17BEND08 | A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar | 2017 | | | |
| V17BEND09 | A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies | 2017 | | | |
| V17BEND10 | A Memristor Based Binary Multiplier | 2017 | | | |
| V17BEND11 | Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications | 2017 | | | |
| V17BEND12 | Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays | 2017 | | | |
| V17BEND13 | Design and Low Power Magnitude Comparator | 2017 | | | |
| V17BEND14 | Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders | 2017 | | | |
| V17BEND15 | Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology | 2017 | | | |
| V17BEND16 | High Performance Ternary Adder using CNTFET | 2017 | | | |
| V17BEND17 | High-performance engineered gate transistor-based compact digital circuits | 2017 | | | |
| V17BEND18 | Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops | 2017 | | | |
| V17BEND19 | Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits | 2017 | | | |
| V17BEND20 | Optimized Memristor-Based Multipliers | 2017 | | | |
| V17BEND21 | Probability-Driven Multibit Flip-Flop Integration With Clock Gating | 2017 | | | |
| V17BEND22 | Register – Less NULL Conventional Logic | 2017 | | | |
| V17BEND23 | Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template | 2017 | | | |
| V17BEND24 | Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design | 2017 | | | |
| V17BEND25 | 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | 2017 | | | |
| V17BEND26 | Fault Tolerant Logic Cell FPGA | 2017 | | | |
